Design Name | cpld |
Device, Speed (SpeedFile Version) | XC9536, -15 (3.0) |
Date Created | Wed Dec 31 09:15:50 2014 |
Created By | Timing Report Generator: version P.68d |
Copyright | Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
---|
Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Performance Summary | |
---|---|
Min. Clock Period | 18.000 ns. |
Max. Clock Frequency (fSYSTEM) | 55.556 MHz. |
Limited by Cycle Time for clk | |
Clock to Setup (tCYC) | 18.000 ns. |
Pad to Pad Delay (tPD) | 15.000 ns. |
Setup to Clock at the Pad (tSU) | 8.000 ns. |
Clock Pad to Output Pad Delay (tCO) | 23.000 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS1000 | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2F | 0.0 | 18.0 | 121 | 121 |
AUTO_TS_P2P | 0.0 | 23.0 | 19 | 19 |
AUTO_TS_P2F | 0.0 | 11.0 | 3 | 3 |
AUTO_TS_F2P | 0.0 | 20.0 | 2 | 2 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
counter<0>.Q to _ipl2.D | 0.000 | 18.000 | -18.000 |
counter<0>.Q to counter<10>.D | 0.000 | 18.000 | -18.000 |
counter<0>.Q to counter<11>.D | 0.000 | 18.000 | -18.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
clk to _ipl1 | 0.000 | 23.000 | -23.000 |
_as to _cerom | 0.000 | 15.000 | -15.000 |
_rxf to _ipl1 | 0.000 | 15.000 | -15.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
fc0 to _ipl2.D | 0.000 | 11.000 | -11.000 |
fc1 to _ipl2.D | 0.000 | 11.000 | -11.000 |
clk to clk_IBUF/FCLK | 0.000 | 3.000 | -3.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
_ipl2.Q to _ipl1 | 0.000 | 20.000 | -20.000 |
_ipl2.Q to _ipl2 | 0.000 | 5.000 | -5.000 |
Clock | fEXT (MHz) | Reason |
---|---|---|
clk | 55.556 | Limited by Cycle Time for clk |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
fc0 | 8.000 | 0.000 |
fc1 | 8.000 | 0.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
_ipl1 | 23.000 |
_ipl2 | 8.000 |
Source | Destination | Delay |
---|---|---|
counter<0>.Q | _ipl2.D | 18.000 |
counter<0>.Q | counter<10>.D | 18.000 |
counter<0>.Q | counter<11>.D | 18.000 |
counter<0>.Q | counter<12>.D | 18.000 |
counter<0>.Q | counter<13>.D | 18.000 |
counter<0>.Q | counter<14>.D | 18.000 |
counter<0>.Q | counter<1>.D | 18.000 |
counter<0>.Q | counter<2>.D | 18.000 |
counter<0>.Q | counter<3>.D | 18.000 |
counter<0>.Q | counter<4>.D | 18.000 |
counter<0>.Q | counter<5>.D | 18.000 |
counter<0>.Q | counter<6>.D | 18.000 |
counter<0>.Q | counter<7>.D | 18.000 |
counter<0>.Q | counter<8>.D | 18.000 |
counter<0>.Q | counter<9>.D | 18.000 |
counter<10>.Q | _ipl2.D | 18.000 |
counter<10>.Q | counter<11>.D | 18.000 |
counter<10>.Q | counter<12>.D | 18.000 |
counter<10>.Q | counter<13>.D | 18.000 |
counter<10>.Q | counter<14>.D | 18.000 |
counter<11>.Q | _ipl2.D | 18.000 |
counter<11>.Q | counter<12>.D | 18.000 |
counter<11>.Q | counter<13>.D | 18.000 |
counter<11>.Q | counter<14>.D | 18.000 |
counter<12>.Q | _ipl2.D | 18.000 |
counter<12>.Q | counter<13>.D | 18.000 |
counter<12>.Q | counter<14>.D | 18.000 |
counter<13>.Q | _ipl2.D | 18.000 |
counter<13>.Q | counter<14>.D | 18.000 |
counter<14>.Q | _ipl2.D | 18.000 |
counter<1>.Q | _ipl2.D | 18.000 |
counter<1>.Q | counter<10>.D | 18.000 |
counter<1>.Q | counter<11>.D | 18.000 |
counter<1>.Q | counter<12>.D | 18.000 |
counter<1>.Q | counter<13>.D | 18.000 |
counter<1>.Q | counter<14>.D | 18.000 |
counter<1>.Q | counter<2>.D | 18.000 |
counter<1>.Q | counter<3>.D | 18.000 |
counter<1>.Q | counter<4>.D | 18.000 |
counter<1>.Q | counter<5>.D | 18.000 |
counter<1>.Q | counter<6>.D | 18.000 |
counter<1>.Q | counter<7>.D | 18.000 |
counter<1>.Q | counter<8>.D | 18.000 |
counter<1>.Q | counter<9>.D | 18.000 |
counter<2>.Q | _ipl2.D | 18.000 |
counter<2>.Q | counter<10>.D | 18.000 |
counter<2>.Q | counter<11>.D | 18.000 |
counter<2>.Q | counter<12>.D | 18.000 |
counter<2>.Q | counter<13>.D | 18.000 |
counter<2>.Q | counter<14>.D | 18.000 |
counter<2>.Q | counter<3>.D | 18.000 |
counter<2>.Q | counter<4>.D | 18.000 |
counter<2>.Q | counter<5>.D | 18.000 |
counter<2>.Q | counter<6>.D | 18.000 |
counter<2>.Q | counter<7>.D | 18.000 |
counter<2>.Q | counter<8>.D | 18.000 |
counter<2>.Q | counter<9>.D | 18.000 |
counter<3>.Q | _ipl2.D | 18.000 |
counter<3>.Q | counter<10>.D | 18.000 |
counter<3>.Q | counter<11>.D | 18.000 |
counter<3>.Q | counter<12>.D | 18.000 |
counter<3>.Q | counter<13>.D | 18.000 |
counter<3>.Q | counter<14>.D | 18.000 |
counter<3>.Q | counter<4>.D | 18.000 |
counter<3>.Q | counter<5>.D | 18.000 |
counter<3>.Q | counter<6>.D | 18.000 |
counter<3>.Q | counter<7>.D | 18.000 |
counter<3>.Q | counter<8>.D | 18.000 |
counter<3>.Q | counter<9>.D | 18.000 |
counter<4>.Q | _ipl2.D | 18.000 |
counter<4>.Q | counter<10>.D | 18.000 |
counter<4>.Q | counter<11>.D | 18.000 |
counter<4>.Q | counter<12>.D | 18.000 |
counter<4>.Q | counter<13>.D | 18.000 |
counter<4>.Q | counter<14>.D | 18.000 |
counter<4>.Q | counter<5>.D | 18.000 |
counter<4>.Q | counter<6>.D | 18.000 |
counter<4>.Q | counter<7>.D | 18.000 |
counter<4>.Q | counter<8>.D | 18.000 |
counter<4>.Q | counter<9>.D | 18.000 |
counter<5>.Q | _ipl2.D | 18.000 |
counter<5>.Q | counter<10>.D | 18.000 |
counter<5>.Q | counter<11>.D | 18.000 |
counter<5>.Q | counter<12>.D | 18.000 |
counter<5>.Q | counter<13>.D | 18.000 |
counter<5>.Q | counter<14>.D | 18.000 |
counter<5>.Q | counter<6>.D | 18.000 |
counter<5>.Q | counter<7>.D | 18.000 |
counter<5>.Q | counter<8>.D | 18.000 |
counter<5>.Q | counter<9>.D | 18.000 |
counter<6>.Q | _ipl2.D | 18.000 |
counter<6>.Q | counter<10>.D | 18.000 |
counter<6>.Q | counter<11>.D | 18.000 |
counter<6>.Q | counter<12>.D | 18.000 |
counter<6>.Q | counter<13>.D | 18.000 |
counter<6>.Q | counter<14>.D | 18.000 |
counter<6>.Q | counter<7>.D | 18.000 |
counter<6>.Q | counter<8>.D | 18.000 |
counter<6>.Q | counter<9>.D | 18.000 |
counter<7>.Q | _ipl2.D | 18.000 |
counter<7>.Q | counter<10>.D | 18.000 |
counter<7>.Q | counter<11>.D | 18.000 |
counter<7>.Q | counter<12>.D | 18.000 |
counter<7>.Q | counter<13>.D | 18.000 |
counter<7>.Q | counter<14>.D | 18.000 |
counter<7>.Q | counter<8>.D | 18.000 |
counter<7>.Q | counter<9>.D | 18.000 |
counter<8>.Q | _ipl2.D | 18.000 |
counter<8>.Q | counter<10>.D | 18.000 |
counter<8>.Q | counter<11>.D | 18.000 |
counter<8>.Q | counter<12>.D | 18.000 |
counter<8>.Q | counter<13>.D | 18.000 |
counter<8>.Q | counter<14>.D | 18.000 |
counter<8>.Q | counter<9>.D | 18.000 |
counter<9>.Q | _ipl2.D | 18.000 |
counter<9>.Q | counter<10>.D | 18.000 |
counter<9>.Q | counter<11>.D | 18.000 |
counter<9>.Q | counter<12>.D | 18.000 |
counter<9>.Q | counter<13>.D | 18.000 |
counter<9>.Q | counter<14>.D | 18.000 |
_ipl2.Q | _ipl2.D | 16.000 |
Source Pad | Destination Pad | Delay |
---|---|---|
_as | _cerom | 15.000 |
_rxf | _ipl1 | 15.000 |
addr<15> | _cerom | 15.000 |
addr<16> | _cerom | 15.000 |
addr<17> | _cerom | 15.000 |
addr<18> | _cerom | 15.000 |
addr<19> | _ceram | 15.000 |
addr<19> | _cerom | 15.000 |
fc0 | _cerom | 15.000 |
fc0 | _dtack | 15.000 |
fc0 | _vpa | 15.000 |
fc1 | _cerom | 15.000 |
fc1 | _dtack | 15.000 |
fc1 | _vpa | 15.000 |
rw | _oe | 15.000 |
button | _halt | 14.000 |
button | _reset | 14.000 |