********** Mapped Logic ********** |
$OpTx$$OpTx$FX_DC$1_INV$21 <= (fc1 AND fc0); |
_ceram <= NOT (((NOT _as AND NOT fc1 AND addr(19))
OR (NOT _as AND NOT fc0 AND addr(19)))); |
_cerom <= ((_as)
OR (addr(19)) OR (fc1 AND fc0) OR (addr(18) AND addr(17) AND addr(16) AND addr(15))); |
_dtack <= (fc1 AND fc0); |
_halt_I <= '0';
_halt <= _halt_I when _halt_OE = '1' else 'Z'; _halt_OE <= NOT buttonReg; |
_ipl1 <= NOT ((NOT _rdf AND _ipl2.PIN)); |
FDCPE__ipl2: FDCPE port map (_ipl2,_ipl2_D,clk,'0','0');
_ipl2_D <= ((NOT fc1 AND NOT _ipl2.PIN) OR (NOT fc0 AND NOT _ipl2.PIN) OR (NOT counter(0) AND NOT counter(10) AND NOT counter(11) AND NOT counter(12) AND NOT counter(13) AND NOT counter(1) AND NOT counter(2) AND NOT counter(3) AND NOT counter(4) AND NOT counter(5) AND NOT counter(6) AND NOT counter(7) AND NOT counter(8) AND NOT counter(9) AND NOT counter(14))); |
_oe <= NOT rw; |
_rd <= NOT (((addr(18) AND addr(17) AND addr(16) AND addr(15) AND
NOT _as AND NOT addr(14) AND NOT fc1 AND NOT addr(19) AND rw AND NOT addr(13)) OR (addr(18) AND addr(17) AND addr(16) AND addr(15) AND NOT _as AND NOT addr(14) AND NOT fc0 AND NOT addr(19) AND rw AND NOT addr(13)))); |
_reset_I <= '0';
_reset <= _reset_I when _reset_OE = '1' else 'Z'; _reset_OE <= NOT buttonReg; |
_vpa <= NOT ((fc1 AND fc0)); |
FTCPE_buttonReg: FTCPE port map (buttonReg,buttonReg_T,clk,'0','0');
buttonReg_T <= ((NOT counter(0) AND buttonReg AND NOT counter(10) AND NOT counter(11) AND NOT counter(12) AND NOT counter(13) AND NOT counter(1) AND NOT counter(2) AND NOT counter(3) AND NOT counter(4) AND NOT counter(5) AND NOT counter(6) AND NOT counter(7) AND NOT counter(8) AND NOT counter(9) AND NOT counter(14) AND NOT button) OR (NOT counter(0) AND NOT buttonReg AND NOT counter(10) AND NOT counter(11) AND NOT counter(12) AND NOT counter(13) AND NOT counter(1) AND NOT counter(2) AND NOT counter(3) AND NOT counter(4) AND NOT counter(5) AND NOT counter(6) AND NOT counter(7) AND NOT counter(8) AND NOT counter(9) AND NOT counter(14) AND button)); |
FTCPE_counter0: FTCPE port map (counter(0),'1',clk,'0','0'); |
FTCPE_counter1: FTCPE port map (counter(1),counter(0),clk,'0','0'); |
FTCPE_counter2: FTCPE port map (counter(2),counter_T(2),clk,'0','0');
counter_T(2) <= (counter(0) AND counter(1)); |
FTCPE_counter3: FTCPE port map (counter(3),counter_T(3),clk,'0','0');
counter_T(3) <= (counter(0) AND counter(1) AND counter(2)); |
FTCPE_counter4: FTCPE port map (counter(4),counter_T(4),clk,'0','0');
counter_T(4) <= (counter(0) AND counter(1) AND counter(2) AND counter(3)); |
FTCPE_counter5: FTCPE port map (counter(5),counter_T(5),clk,'0','0');
counter_T(5) <= (counter(0) AND counter(1) AND counter(2) AND counter(3) AND counter(4)); |
FTCPE_counter6: FTCPE port map (counter(6),counter_T(6),clk,'0','0');
counter_T(6) <= (counter(0) AND counter(1) AND counter(2) AND counter(3) AND counter(4) AND counter(5)); |
FTCPE_counter7: FTCPE port map (counter(7),counter_T(7),clk,'0','0');
counter_T(7) <= (counter(0) AND counter(1) AND counter(2) AND counter(3) AND counter(4) AND counter(5) AND counter(6)); |
FTCPE_counter8: FTCPE port map (counter(8),counter_T(8),clk,'0','0');
counter_T(8) <= (counter(0) AND counter(1) AND counter(2) AND counter(3) AND counter(4) AND counter(5) AND counter(6) AND counter(7)); |
FTCPE_counter9: FTCPE port map (counter(9),counter_T(9),clk,'0','0');
counter_T(9) <= (counter(0) AND counter(1) AND counter(2) AND counter(3) AND counter(4) AND counter(5) AND counter(6) AND counter(7) AND counter(8)); |
FTCPE_counter10: FTCPE port map (counter(10),counter_T(10),clk,'0','0');
counter_T(10) <= (counter(0) AND counter(1) AND counter(2) AND counter(3) AND counter(4) AND counter(5) AND counter(6) AND counter(7) AND counter(8) AND counter(9)); |
FTCPE_counter11: FTCPE port map (counter(11),counter_T(11),clk,'0','0');
counter_T(11) <= (counter(0) AND counter(10) AND counter(1) AND counter(2) AND counter(3) AND counter(4) AND counter(5) AND counter(6) AND counter(7) AND counter(8) AND counter(9)); |
FTCPE_counter12: FTCPE port map (counter(12),counter_T(12),clk,'0','0');
counter_T(12) <= (counter(0) AND counter(10) AND counter(11) AND counter(1) AND counter(2) AND counter(3) AND counter(4) AND counter(5) AND counter(6) AND counter(7) AND counter(8) AND counter(9)); |
FTCPE_counter13: FTCPE port map (counter(13),counter_T(13),clk,'0','0');
counter_T(13) <= (counter(0) AND counter(10) AND counter(11) AND counter(12) AND counter(1) AND counter(2) AND counter(3) AND counter(4) AND counter(5) AND counter(6) AND counter(7) AND counter(8) AND counter(9)); |
FTCPE_counter14: FTCPE port map (counter(14),counter_T(14),clk,'0','0');
counter_T(14) <= (counter(0) AND counter(10) AND counter(11) AND counter(12) AND counter(13) AND counter(1) AND counter(2) AND counter(3) AND counter(4) AND counter(5) AND counter(6) AND counter(7) AND counter(8) AND counter(9)); |
d0_I <= ((addr(12) AND _txe)
OR (NOT addr(12) AND _rdf)); d0 <= d0_I when d0_OE = '1' else 'Z'; d0_OE <= (addr(18) AND addr(17) AND addr(16) AND addr(15) AND NOT _as AND addr(14) AND NOT addr(19) AND rw AND NOT addr(13) AND NOT $OpTx$$OpTx$FX_DC$1_INV$21); |
FTCPE_status_led: FTCPE port map (status_led,status_led_T,clk,'0','0');
status_led_T <= ((addr(18) AND addr(17) AND addr(16) AND addr(15) AND NOT _ds AND NOT _as AND addr(14) AND NOT fc1 AND NOT addr(19) AND NOT rw AND addr(13) AND d0.PIN AND NOT status_led.PIN) OR (addr(18) AND addr(17) AND addr(16) AND addr(15) AND NOT _ds AND NOT _as AND addr(14) AND NOT fc1 AND NOT addr(19) AND NOT rw AND addr(13) AND NOT d0.PIN AND status_led.PIN) OR (addr(18) AND addr(17) AND addr(16) AND addr(15) AND NOT _ds AND NOT _as AND addr(14) AND NOT fc0 AND NOT addr(19) AND NOT rw AND addr(13) AND d0.PIN AND NOT status_led.PIN) OR (addr(18) AND addr(17) AND addr(16) AND addr(15) AND NOT _ds AND NOT _as AND addr(14) AND NOT fc0 AND NOT addr(19) AND NOT rw AND addr(13) AND NOT d0.PIN AND status_led.PIN)); |
wr <= ((addr(18) AND addr(17) AND addr(16) AND addr(15) AND
NOT _ds AND NOT _as AND NOT addr(14) AND NOT fc1 AND NOT addr(19) AND NOT rw AND addr(13)) OR (addr(18) AND addr(17) AND addr(16) AND addr(15) AND NOT _ds AND NOT _as AND NOT addr(14) AND NOT fc0 AND NOT addr(19) AND NOT rw AND addr(13))); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |