cpldfit:  version P.68d                             Xilinx Inc.
                                  Fitter Report
Design Name: cpld                                Date:  1-13-2015,  5:35PM
Device Used: XC9536-15-VQ44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
30 /36  ( 83%) 43  /180  ( 24%) 64 /72  ( 89%)   18 /36  ( 50%) 30 /34  ( 88%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1          12/18       33/36       33          16/90       8/17
FB2          18/18*      31/36       31          27/90       5/17
             -----       -----                   -----       -----     
             30/36       64/72                   43/180     13/34 

* - Resource is exhausted

** Global Control Resources **

Signal 'clk' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   16          16    |  I/O              :    25      28
Output        :   10          10    |  GCK/IO           :     3       3
Bidirectional :    3           3    |  GTS/IO           :     1       2
GCK           :    1           1    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     30          30

** Power Data **

There are 30 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'cpld.ise'.
INFO:Cpld - Inferring BUFG constraint for signal '_txe' based upon the LOC
   constraint 'P43'. It is recommended that you declare this BUFG explicitedly
   in your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
INFO:Cpld - Inferring BUFG constraint for signal 'clk' based upon the LOC
   constraint 'P1'. It is recommended that you declare this BUFG explicitedly in
   your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
INFO:Cpld - Inferring BUFG constraint for signal 'd0' based upon the LOC
   constraint 'P44'. It is recommended that you declare this BUFG explicitedly
   in your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'N01' is
   ignored. Most likely the signal is gated and therefore cannot be used as a
   global control signal.
WARNING:Cpld:1239 - The global clock designation (BUFG) on signal '&txe_IBUF' is
   ignored. Most likely the signal is gated and therefore cannot be used as a
   global control signal.
*************************  Summary of Mapped Logic  ************************

** 13 Outputs **

Signal                      Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                        Pts   Inps          No.  Type    Use     Mode Rate State
wr                          2     12    FB1_1   40   I/O     O       STD  FAST 
d0                          3     13    FB1_5   44   GCK/I/O I/O     STD  FAST 
_dtack                      1     2     FB1_11  7    I/O     O       STD  FAST 
_halt                       1     1     FB1_12  8    I/O     O       STD  FAST 
_reset                      1     1     FB1_13  12   I/O     O       STD  FAST 
_vpa                        1     2     FB1_14  13   I/O     O       STD  FAST 
_ipl1                       1     2     FB1_15  14   I/O     O       STD  FAST 
_ipl2                       3     18    FB1_17  18   I/O     I/O     STD  FAST RESET
_rd                         2     11    FB2_1   39   I/O     O       STD  FAST 
_ceram                      2     4     FB2_5   34   GTS/I/O O       STD  FAST 
_cerom                      4     8     FB2_6   33   GSR/I/O O       STD  FAST 
_oe                         1     1     FB2_14  22   I/O     O       STD  FAST 
status_led                  4     14    FB2_16  20   I/O     I/O     STD  FAST RESET

** 17 Buried Nodes **

Signal                      Total Total Loc     Pwr  Reg Init
Name                        Pts   Inps          Mode State
counter<3>                  1     3     FB1_9   STD  RESET
counter<2>                  1     2     FB1_10  STD  RESET
counter<1>                  1     1     FB1_16  STD  RESET
counter<0>                  0     0     FB1_18  STD  RESET
counter<9>                  1     9     FB2_2   STD  RESET
counter<8>                  1     8     FB2_3   STD  RESET
counter<7>                  1     7     FB2_4   STD  RESET
counter<6>                  1     6     FB2_7   STD  RESET
counter<5>                  1     5     FB2_8   STD  RESET
counter<4>                  1     4     FB2_9   STD  RESET
counter<14>                 1     14    FB2_10  STD  RESET
counter<13>                 1     13    FB2_11  STD  RESET
counter<12>                 1     12    FB2_12  STD  RESET
counter<11>                 1     11    FB2_13  STD  RESET
counter<10>                 1     10    FB2_15  STD  RESET
$OpTx$$OpTx$FX_DC$1_INV$21  1     2     FB2_17  STD  
buttonReg                   2     17    FB2_18  STD  RESET

** 17 Inputs **

Signal                      Loc     Pin  Pin     Pin     
Name                                No.  Type    Use     
_rdf                        FB1_2   41   I/O     I
_txe                        FB1_3   43   GCK/I/O I
addr<19>                    FB1_4   42   I/O     I
addr<18>                    FB1_6   2    I/O     I
clk                         FB1_7   1    GCK/I/O GCK
addr<17>                    FB1_8   3    I/O     I
_ds                         FB1_9   5    I/O     I
rw                          FB1_10  6    I/O     I
fc0                         FB1_16  16   I/O     I
_as                         FB2_2   38   I/O     I
addr<12>                    FB2_4   37   I/O     I
addr<13>                    FB2_7   32   I/O     I
addr<14>                    FB2_8   31   I/O     I
addr<15>                    FB2_9   30   I/O     I
addr<16>                    FB2_10  29   I/O     I
button                      FB2_15  21   I/O     I
fc1                         FB2_17  19   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               33/3
Number of signals used by logic mapping into function block:  33
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
wr                    2       0     0   3     FB1_1   40    I/O     O
(unused)              0       0     0   5     FB1_2   41    I/O     I
(unused)              0       0     0   5     FB1_3   43    GCK/I/O I
(unused)              0       0     0   5     FB1_4   42    I/O     I
d0                    3       0     0   2     FB1_5   44    GCK/I/O I/O
(unused)              0       0     0   5     FB1_6   2     I/O     I
(unused)              0       0     0   5     FB1_7   1     GCK/I/O GCK
(unused)              0       0     0   5     FB1_8   3     I/O     I
counter<3>            1       0     0   4     FB1_9   5     I/O     I
counter<2>            1       0     0   4     FB1_10  6     I/O     I
_dtack                1       0     0   4     FB1_11  7     I/O     O
_halt                 1       0     0   4     FB1_12  8     I/O     O
_reset                1       0     0   4     FB1_13  12    I/O     O
_vpa                  1       0     0   4     FB1_14  13    I/O     O
_ipl1                 1       0     0   4     FB1_15  14    I/O     O
counter<1>            1       0     0   4     FB1_16  16    I/O     I
_ipl2                 3       0     0   2     FB1_17  18    I/O     I/O
counter<0>            0       0     0   5     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$$OpTx$FX_DC$1_INV$21  12: addr<17>          23: counter<2> 
  2: _as                         13: addr<18>          24: counter<3> 
  3: _ds                         14: addr<19>          25: counter<4> 
  4: _rdf                        15: buttonReg         26: counter<5> 
  5: _txe                        16: counter<0>        27: counter<6> 
  6: _ipl2.PIN                   17: counter<10>       28: counter<7> 
  7: addr<12>                    18: counter<11>       29: counter<8> 
  8: addr<13>                    19: counter<12>       30: counter<9> 
  9: addr<14>                    20: counter<13>       31: fc0 
 10: addr<15>                    21: counter<14>       32: fc1 
 11: addr<16>                    22: counter<1>        33: rw 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
wr                   .XX....XXXXXXX................XXX....... 12      12
d0                   XX.XX.XXXXXXXX..................X....... 13      13
counter<3>           ...............X.....XX................. 3       3
counter<2>           ...............X.....X.................. 2       2
_dtack               ..............................XX........ 2       2
_halt                ..............X......................... 1       1
_reset               ..............X......................... 1       1
_vpa                 ..............................XX........ 2       2
_ipl1                ...X.X.................................. 2       2
counter<1>           ...............X........................ 1       1
_ipl2                .....X.........XXXXXXXXXXXXXXXXX........ 18      18
counter<0>           ........................................ 0       0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               31/5
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
_rd                   2       0     0   3     FB2_1   39    I/O     O
counter<9>            1       0     0   4     FB2_2   38    I/O     I
counter<8>            1       0     0   4     FB2_3   36    GTS/I/O (b)
counter<7>            1       0     0   4     FB2_4   37    I/O     I
_ceram                2       0     0   3     FB2_5   34    GTS/I/O O
_cerom                4       0     0   1     FB2_6   33    GSR/I/O O
counter<6>            1       0     0   4     FB2_7   32    I/O     I
counter<5>            1       0     0   4     FB2_8   31    I/O     I
counter<4>            1       0     0   4     FB2_9   30    I/O     I
counter<14>           1       0     0   4     FB2_10  29    I/O     I
counter<13>           1       0     0   4     FB2_11  28    I/O     (b)
counter<12>           1       0     0   4     FB2_12  27    I/O     (b)
counter<11>           1       0     0   4     FB2_13  23    I/O     (b)
_oe                   1       0     0   4     FB2_14  22    I/O     O
counter<10>           1       0     0   4     FB2_15  21    I/O     I
status_led            4       0     0   1     FB2_16  20    I/O     I/O
$OpTx$$OpTx$FX_DC$1_INV$21
                      1       0     0   4     FB2_17  19    I/O     I
buttonReg             2       0     0   3     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: _as               12: button            22: counter<4> 
  2: _ds               13: counter<0>        23: counter<5> 
  3: d0.PIN            14: counter<10>       24: counter<6> 
  4: addr<13>          15: counter<11>       25: counter<7> 
  5: addr<14>          16: counter<12>       26: counter<8> 
  6: addr<15>          17: counter<13>       27: counter<9> 
  7: addr<16>          18: counter<14>       28: fc0 
  8: addr<17>          19: counter<1>        29: fc1 
  9: addr<18>          20: counter<2>        30: rw 
 10: addr<19>          21: counter<3>        31: status_led.PIN 
 11: buttonReg        

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
_rd                  X..XXXXXXX.................XXX.......... 11      11
counter<9>           ............X.....XXXXXXXX.............. 9       9
counter<8>           ............X.....XXXXXXX............... 8       8
counter<7>           ............X.....XXXXXX................ 7       7
_ceram               X........X.................XX........... 4       4
_cerom               X....XXXXX.................XX........... 8       8
counter<6>           ............X.....XXXXX................. 6       6
counter<5>           ............X.....XXXX.................. 5       5
counter<4>           ............X.....XXX................... 4       4
counter<14>          ............XXXXX.XXXXXXXXX............. 14      14
counter<13>          ............XXXX..XXXXXXXXX............. 13      13
counter<12>          ............XXX...XXXXXXXXX............. 12      12
counter<11>          ............XX....XXXXXXXXX............. 11      11
_oe                  .............................X.......... 1       1
counter<10>          ............X.....XXXXXXXXX............. 10      10
status_led           XXXXXXXXXX.................XXXX......... 14      14
$OpTx$$OpTx$FX_DC$1_INV$21 
                     ...........................XX........... 2       2
buttonReg            ..........XXXXXXXXXXXXXXXXX............. 17      17
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


$OpTx$$OpTx$FX_DC$1_INV$21 <= (fc1 AND fc0);


_ceram <= NOT (((NOT _as AND NOT fc1 AND addr(19))
	OR (NOT _as AND NOT fc0 AND addr(19))));


_cerom <= ((_as)
	OR (addr(19))
	OR (fc1 AND fc0)
	OR (addr(18) AND addr(17) AND addr(16) AND addr(15)));


_dtack <= (fc1 AND fc0);


_halt_I <= '0';
_halt <= _halt_I when _halt_OE = '1' else 'Z';
_halt_OE <= NOT buttonReg;


_ipl1 <= NOT ((NOT _rdf AND _ipl2.PIN));

FDCPE__ipl2: FDCPE port map (_ipl2,_ipl2_D,clk,'0','0');
_ipl2_D <= ((NOT fc1 AND NOT _ipl2.PIN)
	OR (NOT fc0 AND NOT _ipl2.PIN)
	OR (NOT counter(0) AND NOT counter(10) AND NOT counter(11) AND 
	NOT counter(12) AND NOT counter(13) AND NOT counter(1) AND NOT counter(2) AND 
	NOT counter(3) AND NOT counter(4) AND NOT counter(5) AND NOT counter(6) AND 
	NOT counter(7) AND NOT counter(8) AND NOT counter(9) AND NOT counter(14)));


_oe <= NOT rw;


_rd <= NOT (((addr(18) AND addr(17) AND addr(16) AND addr(15) AND 
	NOT _as AND NOT addr(14) AND NOT fc1 AND NOT addr(19) AND rw AND NOT addr(13))
	OR (addr(18) AND addr(17) AND addr(16) AND addr(15) AND 
	NOT _as AND NOT addr(14) AND NOT fc0 AND NOT addr(19) AND rw AND NOT addr(13))));


_reset_I <= '0';
_reset <= _reset_I when _reset_OE = '1' else 'Z';
_reset_OE <= NOT buttonReg;


_vpa <= NOT ((fc1 AND fc0));

FTCPE_buttonReg: FTCPE port map (buttonReg,buttonReg_T,clk,'0','0');
buttonReg_T <= ((NOT counter(0) AND buttonReg AND NOT counter(10) AND 
	NOT counter(11) AND NOT counter(12) AND NOT counter(13) AND NOT counter(1) AND 
	NOT counter(2) AND NOT counter(3) AND NOT counter(4) AND NOT counter(5) AND 
	NOT counter(6) AND NOT counter(7) AND NOT counter(8) AND NOT counter(9) AND 
	NOT counter(14) AND NOT button)
	OR (NOT counter(0) AND NOT buttonReg AND NOT counter(10) AND 
	NOT counter(11) AND NOT counter(12) AND NOT counter(13) AND NOT counter(1) AND 
	NOT counter(2) AND NOT counter(3) AND NOT counter(4) AND NOT counter(5) AND 
	NOT counter(6) AND NOT counter(7) AND NOT counter(8) AND NOT counter(9) AND 
	NOT counter(14) AND button));

FTCPE_counter0: FTCPE port map (counter(0),'1',clk,'0','0');

FTCPE_counter1: FTCPE port map (counter(1),counter(0),clk,'0','0');

FTCPE_counter2: FTCPE port map (counter(2),counter_T(2),clk,'0','0');
counter_T(2) <= (counter(0) AND counter(1));

FTCPE_counter3: FTCPE port map (counter(3),counter_T(3),clk,'0','0');
counter_T(3) <= (counter(0) AND counter(1) AND counter(2));

FTCPE_counter4: FTCPE port map (counter(4),counter_T(4),clk,'0','0');
counter_T(4) <= (counter(0) AND counter(1) AND counter(2) AND 
	counter(3));

FTCPE_counter5: FTCPE port map (counter(5),counter_T(5),clk,'0','0');
counter_T(5) <= (counter(0) AND counter(1) AND counter(2) AND 
	counter(3) AND counter(4));

FTCPE_counter6: FTCPE port map (counter(6),counter_T(6),clk,'0','0');
counter_T(6) <= (counter(0) AND counter(1) AND counter(2) AND 
	counter(3) AND counter(4) AND counter(5));

FTCPE_counter7: FTCPE port map (counter(7),counter_T(7),clk,'0','0');
counter_T(7) <= (counter(0) AND counter(1) AND counter(2) AND 
	counter(3) AND counter(4) AND counter(5) AND counter(6));

FTCPE_counter8: FTCPE port map (counter(8),counter_T(8),clk,'0','0');
counter_T(8) <= (counter(0) AND counter(1) AND counter(2) AND 
	counter(3) AND counter(4) AND counter(5) AND counter(6) AND 
	counter(7));

FTCPE_counter9: FTCPE port map (counter(9),counter_T(9),clk,'0','0');
counter_T(9) <= (counter(0) AND counter(1) AND counter(2) AND 
	counter(3) AND counter(4) AND counter(5) AND counter(6) AND 
	counter(7) AND counter(8));

FTCPE_counter10: FTCPE port map (counter(10),counter_T(10),clk,'0','0');
counter_T(10) <= (counter(0) AND counter(1) AND counter(2) AND 
	counter(3) AND counter(4) AND counter(5) AND counter(6) AND 
	counter(7) AND counter(8) AND counter(9));

FTCPE_counter11: FTCPE port map (counter(11),counter_T(11),clk,'0','0');
counter_T(11) <= (counter(0) AND counter(10) AND counter(1) AND 
	counter(2) AND counter(3) AND counter(4) AND counter(5) AND 
	counter(6) AND counter(7) AND counter(8) AND counter(9));

FTCPE_counter12: FTCPE port map (counter(12),counter_T(12),clk,'0','0');
counter_T(12) <= (counter(0) AND counter(10) AND counter(11) AND 
	counter(1) AND counter(2) AND counter(3) AND counter(4) AND 
	counter(5) AND counter(6) AND counter(7) AND counter(8) AND 
	counter(9));

FTCPE_counter13: FTCPE port map (counter(13),counter_T(13),clk,'0','0');
counter_T(13) <= (counter(0) AND counter(10) AND counter(11) AND 
	counter(12) AND counter(1) AND counter(2) AND counter(3) AND 
	counter(4) AND counter(5) AND counter(6) AND counter(7) AND 
	counter(8) AND counter(9));

FTCPE_counter14: FTCPE port map (counter(14),counter_T(14),clk,'0','0');
counter_T(14) <= (counter(0) AND counter(10) AND counter(11) AND 
	counter(12) AND counter(13) AND counter(1) AND counter(2) AND 
	counter(3) AND counter(4) AND counter(5) AND counter(6) AND 
	counter(7) AND counter(8) AND counter(9));


d0_I <= ((addr(12) AND _txe)
	OR (NOT addr(12) AND _rdf));
d0 <= d0_I when d0_OE = '1' else 'Z';
d0_OE <= (addr(18) AND addr(17) AND addr(16) AND addr(15) AND 
	NOT _as AND addr(14) AND NOT addr(19) AND rw AND NOT addr(13) AND 
	NOT $OpTx$$OpTx$FX_DC$1_INV$21);

FTCPE_status_led: FTCPE port map (status_led,status_led_T,clk,'0','0');
status_led_T <= ((addr(18) AND addr(17) AND addr(16) AND addr(15) AND 
	NOT _ds AND NOT _as AND addr(14) AND NOT fc1 AND NOT addr(19) AND NOT rw AND 
	addr(13) AND d0.PIN AND NOT status_led.PIN)
	OR (addr(18) AND addr(17) AND addr(16) AND addr(15) AND 
	NOT _ds AND NOT _as AND addr(14) AND NOT fc1 AND NOT addr(19) AND NOT rw AND 
	addr(13) AND NOT d0.PIN AND status_led.PIN)
	OR (addr(18) AND addr(17) AND addr(16) AND addr(15) AND 
	NOT _ds AND NOT _as AND addr(14) AND NOT fc0 AND NOT addr(19) AND NOT rw AND 
	addr(13) AND d0.PIN AND NOT status_led.PIN)
	OR (addr(18) AND addr(17) AND addr(16) AND addr(15) AND 
	NOT _ds AND NOT _as AND addr(14) AND NOT fc0 AND NOT addr(19) AND NOT rw AND 
	addr(13) AND NOT d0.PIN AND status_led.PIN));


wr <= ((addr(18) AND addr(17) AND addr(16) AND addr(15) AND 
	NOT _ds AND NOT _as AND NOT addr(14) AND NOT fc1 AND NOT addr(19) AND NOT rw AND 
	addr(13))
	OR (addr(18) AND addr(17) AND addr(16) AND addr(15) AND 
	NOT _ds AND NOT _as AND NOT addr(14) AND NOT fc0 AND NOT addr(19) AND NOT rw AND 
	addr(13)));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9536-15-VQ44


   --------------------------------  
  /44 43 42 41 40 39 38 37 36 35 34 \
 | 1                             33 | 
 | 2                             32 | 
 | 3                             31 | 
 | 4                             30 | 
 | 5         XC9536-15-VQ44      29 | 
 | 6                             28 | 
 | 7                             27 | 
 | 8                             26 | 
 | 9                             25 | 
 | 10                            24 | 
 | 11                            23 | 
 \ 12 13 14 15 16 17 18 19 20 21 22 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 clk                              23 TIE                           
  2 addr<18>                         24 TDO                           
  3 addr<17>                         25 GND                           
  4 GND                              26 VCC                           
  5 _ds                              27 TIE                           
  6 rw                               28 TIE                           
  7 _dtack                           29 addr<16>                      
  8 _halt                            30 addr<15>                      
  9 TDI                              31 addr<14>                      
 10 TMS                              32 addr<13>                      
 11 TCK                              33 _cerom                        
 12 _reset                           34 _ceram                        
 13 _vpa                             35 VCC                           
 14 _ipl1                            36 TIE                           
 15 VCC                              37 addr<12>                      
 16 fc0                              38 _as                           
 17 GND                              39 _rd                           
 18 _ipl2                            40 wr                            
 19 fc1                              41 _rdf                          
 20 status_led                       42 addr<19>                      
 21 button                           43 _txe                          
 22 _oe                              44 d0                            


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9536-15-VQ44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25