cpld Project Status (01/13/2015 - 17:35:37)
Project File: CPLD.xise Parser Errors: No Errors
Module Name: cpld Implementation State: Fitted
Target Device: xc9536-15VQ44
  • Errors:
No Errors
Product Version:ISE 14.6
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Jan 13 17:35:19 2015000
Translation ReportCurrentTue Jan 13 17:35:24 2015000
CPLD Fitter Report (Text)CurrentTue Jan 13 17:35:29 201503 Warnings (2 new)3 Infos (3 new)
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Fit Simulation Model Report  

Date Generated: 01/13/2015 - 17:35:37