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Xilinx Memory Controller

I think I’m about ready to crush this Xilinx starter kit under my boot, and use the pulverized component dust to scrub my toilet. That’s not quite fair, though, as my frustration isn’t really with the hardware, but with the inexplicable Xilinx software. At this point, I’ve spent about 20 hours over a couple of weeks, just trying to instantiate the sample Xilinx SDRAM memory controller. I’m amazed that something so central to the use of a Xilinx FPGA or starter kit could be so obtuse. Or maybe it’s me that’s obtuse, but regardless, I was never so exasperated in all the time I was working on BMOW. Back then, at least each piece of hardware was small and understandable, and any errors were of my own making. Now I’m spending hour upon hour attempting to decode the error messages from Xilinx’s software, and trying to guess at how they intended this process to work. I expected something like:

  1. Create new project
  2. Run “memory interface generator” wizard (which Xilinx calls the M.I.G.)
  3. Choose memory type, speed, etc.
  4. The wizard adds some auto-generated .v and .ucf (user constraints) files to my project
  5. Optionally, wizard also adds a test bench, or some kind of example
  6. Synthesize the example, program it to the starter kit, and blink some LEDs to show that it worked.

That was the theory anyway. The reality has been a long series of software errors and omissions too dull to recount in detail. The short version is that when I use the MIG to generate an interface specifically for the Spartan 3A starter kit, the MIG crashes. If I follow some hazy instructions for manually adding the reference design to the project without using the MIG, then I get something that fails the “translate” step. If I use the MIG to generate a new interface design for a board that just happens to have the same hardware as the Spartan 3A starter kit, I also get something that fails the “translate” step. In either case, before the fatal errors, there are many warnings saying that dozens of flip-flops were determined to have a constant 0 or 1 value, and so were optimized away, as well as copious other warnings. Clearly I’m doing something very wrong, but creating a sample design using the reference memory interface on the reference board seems like it should be about as simple a case as it’s possible to get.

I would have given up on it a while ago, except that with no memory interface, there can be no 3D Graphics Thingy. This simply must be made to work in order for the project to progress any further. Unfortunately I’m about out of ideas. I need to find a simple walk-through tutorial that starts with “open ISE, press the New Project button” and finishes with happy green checkmarks next to all the steps in the processes window for an example design using the MIG controller. There are only about 10 mouse clicks needed between that start and finish, so it would seem hard to mess it up much. Either I’m doing something basic wrong, or omitting something, or my computer is haunted. With luck, it will become clear tomorrow.

Read 8 comments and join the conversation 

8 Comments so far

  1. Chris July 5th, 2009 10:26 pm

    Hi Steve,

    Have you found any clues from looking at a DDR2 SDRAM reference design?

    http://www.xilinx.com/products/boards/s3astarter/reference_designs.htm

    Scroll down to DDR2 “Demonstration”.

    I have just received my Spartan 3A starter kit and want to build and prototype a Memory Bus Eavesdropping Tool, so I’ll need to first set up a sdram controller. I stumbled onto your website while doing a internet search.

    I hope to follow your progress.

    Regards

    Chris

  2. Merlin Skinner July 5th, 2009 11:09 pm

    I tinkered with Xilinx stuff years ago and came to much the same conclusion as you. The hardware looks good, but the software was truly horrible. Since then, I’ve used Altera FPGAs and software. While I can’t say the experience has been perfect, life has certainly been easier since!

    Good luck!

    Merlin

  3. John July 6th, 2009 2:08 am

    Sorry to hear you are having such trouble with the SW.
    Have you tried the latest 11.1 release? – I have and it seems to be much better on all fronts.

    I imagine the translate errors you are getting may be due to the .ucf that you are using – if it is one from another device/board, then there may be pin (LOC) or area constraints that are not valid for your device/board, and this will cause translate to fail – so maybe take a look there first.

    As for the registers being removed, that is totally fine – ISE does an excellent job of removing redundant logic, and I’ve yet to see it make a mistake in this department. It can look daunting when you see so many warnings in your logfile, but really this warning is benign.

    The tools can take some time getting used to – but I assure you items like the translate error you mention should be fixable. Try posting the issue you are seeing on forums.xilinx.com or the newsgroup comp.arch.fpga – I’m sure someone there can quickly resolve your issue.

  4. Steve July 6th, 2009 6:19 am

    Wow, Xilinx just denied my request to create a WebCase account for support. They just look better and better each day. I’d registered as a student, which seemed the closest thing to hobbyist or non-commercial. I guess I should go back and lie…

  5. Steve July 6th, 2009 6:34 am

    Hi Chris– I did see that “reference design” too, but it’s actually not a reference design for the Spartan 3A kit, it’s a demonstration of pushing the DDR2 RAM to 200MHz. It requires a -5 speed grade part, where the starter kit only has -4. The docs say it will probably work on the -4 part too, at room temperature and with ideal power conditions. But that seems like more of a novelty than something to base a new design around.

    Merlin– several times I have almost thrown in the towel and ordered an Altera starter kit. I’ve been playing with their Quartus II software too, and while it does feel a little more obvious how to use, the difference didn’t seem large enough to be worth abandoning the time investment I’ve made in learning the Xilinx software. Maybe I should give it one more look.

    John– I’m using ISE WebPack 11.2, and the ucf that’s specifically for the Spartan 3A starter kit. I suspect that if I had a better grasp of the fundamentals here, I’d be able to troubleshoot those translate errors, but right now it’s beyond me. I don’t have the errors here now, but it was something about a net sometopthing/middle/leaf not being found. I went as far as poking through the Verilog files to confirm that sometopthing/middle/leaf did actually exist, but didn’t know what else to do from there.

    I posted a question to forums.xilinx.com a couple of days ago, and received one reply suggesting that I hope a WebCase. Which I can’t do, sadly, because Xilinx denied my request for a WebCase account. I haven’t tried comp.arch.fpga though– I’ll check that out.

    I did finally achieve a small bit of progress despite all these setbacks– see my more recent posting http://www.bigmessowires.com/2009/07/05/small-progress/

  6. Steve November 13th, 2009 3:30 pm

    Yeah, I played with Xilinx stuff a couple of years ago, and even got the Spartan-3E starter kit. What I learned was that I was really disappointed with my choice and that Altera was much nicer to hobbyists. Shortly after, I found fpga4fun.com and bought a Pluto-II from their sister site. The Altera software seemed pretty good and Altera was even nice enough to send me some samples of their Cyclone-II FPGAs for playing around with. All-in-all seemed like a much better company.

  7. naira September 1st, 2012 9:18 am

    hello….
    you have really wonderful information …

    i also try to make a 3D project and i need to ask you if you have any idea about spartan6 sp601 MIG examples on VHDL because i spent many month in it with an error in signals synchronization problem…

    thanks in advance

  8. Mozay May 25th, 2013 10:32 am

    hi Steve,
    this topic is old but i hope you see this post. i am also trying to implemet the interface with spartan 3a starter kit ddr2 sdram but i could not have any progress. If you done this interface, would you please make the source available publicly ?

    I would very much be appreciated.

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