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I think I’m making life more difficult than it needs to be, trying to get this DDR2 SDRAM interface to work. It’s not that the logical interface is so complicated, really… you set your row and column addresses, do a burst transaction, check for refresh… not trivial, but not rocket science either. And the Xilinx MIG or other vendor-specific wizard will generate a memory interface for you to use as a starting point.No, what seems to be difficult is that the margin for error with DDR2 SDRAM is much smaller than with SRAM or plain (single data rate) SDRAM. The voltages are lower, the timing tolerances are tighter, and much more care must be given to compensating for things like possible skew, processes variation between different FPGAs, power supply tolerances, and a host of other worries.I’ve been reading a LOT on this topic in the past couple of weeks, and I’ve been struck by one thing. Except for my Xilinx Spartan 3A starter board, and Altera’s comperable Cyclone III board, I’ve seen zero boards that use DDR or DDR2 memory. The all use plain SDR SDRAM, also known as PC100 or PC133 depending on the speed. I looked at boards in the $150 to $300 range from Opal Kelly, KNJN, XESS, and others, and they all use plain SDR SDRAM. Maybe I should take a hint?Meanwhile, I’ve been digesting as much FPGA documentation as I can. So far I’ve chewed through about 1500 pages of the Xilinx MIG user manual, Spartan 3 series user manual, and Spartan 3A addendum, and I’m midway through the comprehensive book FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version. It’s the best “getting started” reference I’ve seen yet, with good coverage of Verilog, FPGA hardware, and the Xilinx software tools.

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10 Comments so far

  1. Nick Maich - July 29th, 2009 7:04 pm

    I have a similar problem. I’m trying to get my spartan 3e board to work with the output from MIG but its not working at all. How did you get it to work using Leo’s modules? I tried that but I got so many errors every time I tried it. Im using MIG 2.1 and this is the second week I’ve been toiling on this. I just want to see something (even if its an error led light up – that would be okay at this point).
    BTW, I second that comment about the FPGA Prototyping by Verilog book. Simply awesome!

  2. Steve - July 29th, 2009 8:19 pm

    I’m not sure what you meant by Leo’s modules, but let me know what problem you’re seeing with the MIG output, and I’ll try to help. I still don’t have a working demo yet myself, but I think I mostly understand things well enough now to create one.

  3. Nick Maich - July 29th, 2009 9:18 pm

    Hi Steve. I meant Leo Silvestri’s modules (the small progress post). Well, I followed the directions (replaced the top module with his, copied the rest of the source modules to the rtl folder, updated the *.prj file and updated the UCF file to include the LED and LCD signals) but when I click on ise_flow.bat…

    Applying constraints in “vlog_bl2cl25.ucf” to the design…
    Resolving constraint associations…
    Checking Constraint Associations…
    ERROR:ConstraintSystem:58 – Constraint
    [vlog_bl2cl25.ucf(32)]: NET “main_00/top0/data_path0/dqs_delayed_col*” does
    not match any design objects.
    WARNING:ConstraintSystem:56 – Constraint [vlog_bl2cl25.ucf(33)]: Unable to find an
    active ‘TimeGrp’ or ‘TNM’ or ‘TPSync’ or ‘TPThru’ constraint named ‘dqs_clk’.

    WARNING:ConstraintSystem:56 – Constraint [vlog_bl2cl25.ucf(36)]: Unable to find an
    active ‘TimeGrp’ or ‘TNM’ or ‘TPSync’ or ‘TPThru’ constraint named ‘dqs_clk’.

    ERROR:ConstraintSystem:58 – Constraint
    [vlog_bl2cl25.ucf(38)]: NET
    “main_00/top0/data_path0/data_read0/strobe*/wclk*” does not match any design

    This happens for various signals for about 123 times. Thing is, in the generated ddr design code, in the respective modules, I can see these signals. Man, should it be this hard?? I’m beginning to wonder whether the memory is shot (I mean, why else would it not work after so many tries – all designs generated by Xilinx’ tools?).

    Before these errors are reported, the timing report shows that the design would not work (Minimum period: 14.561ns (Maximum Frequency: 68.676MHz)) so for sure it fails on the timing constraints.

    Did you encounter this? Any help is appreciated man. I’m working on a somewhat related project and without memory – there is nothing to show. Thanks!

  4. Steve - July 30th, 2009 6:49 am

    I think I can help, and I ran into the same problem myself.

    Right-click on “Simulate Post-Place and Route” to view its properties, and under “Simulation Model”, make sure the checkbox for “Retain Hierarchy” is checked. If you don’t see it there, look for a similarly-named checkbox under one of the other property dialogs.

    What seems to be happening is that the UCF constraint file refers to signals by their hierarchical name, but by default, the design hierarchy information is thrown away when the HDL is synthesized.

  5. Nick Maich - July 30th, 2009 10:04 am

    Yeah those errors are with that checkbox already checked. Also, prior to using the GUI, I tried to just run the batch script and it still gave me the same errors. Since you got yours to work, would you please point out the error I’m making in the steps below.

    1. Create a reference controller (spartan 3e) using MIG.

    2. Download the zip file from Leo’s site and unzip them in the rtl folder.

    3. Replace the top level module (vlog_bl2cl2.v) with Leo’s (I think he calls it main_00). In my case, I just deleted the contents of the top level and cut and pasted Leo’s code in it (to avoid the ‘missing top level vlog_bl2cl2.v module’ error). So at this point, I have the same file name for the top level as generated by MIG but the contents are Leo’s top level module.

    4. Update the synth/vlog_bl2cl2.prj file to include compilation of all the lcd modules.

    5. Updated the MIG generated ucf file to include the LED and LCD signals.

    6. Click on ise_flow.bat

    These are the steps I’m following. Is there something that I’m missing or I’m doing wrong? With these steps, I get the ‘Maximum Frequency: 68.676MHz’ and also all the 123 errors. Note that I’m not running the ISE GUI, just the batch file. Thanks Steve

  6. Steve - July 30th, 2009 11:03 pm

    Ah, ok. I didn’t actually use Leo’s module, I just used his suggestions. The controller I finally got to synthesize was the MIG-generated one, specifically the reference design for the Spartan 3A Starter Kit. After enabling “retain hierarchy”, and also removing all the references to the ChipScope logic anaylzer stuff, it worked.

  7. Jii - September 9th, 2009 10:51 pm

    Hey Steve, a group of us seniors here at DigiPen are developing our own handheld console, and we’re using an FPGA (Cyclone 3) in place of a graphics chip. We found your site while doing research, and we really appreciate you documenting your progress. Right now we’re designing the pipeline on the FPGA, and we’re running into the same bandwidth concerns that you mentioned a couple posts ago, although we should be able to pull through by running some memory accesses in parallel by having multiple ICs.

    Keep on truckin!

  8. Steve - September 10th, 2009 6:13 am

    Awesome, keep me posted on your progress! I assume you’re designing your own custom board, then? My conclusion on bandwidth is that it’s better to get something that works slowly, then tear out my hair trying to build something fast and complex that never gets off the ground.

  9. Polprav - October 11th, 2009 3:21 pm

    Hello from Russia)

  10. sivasankar - August 12th, 2015 4:09 am

    code for DDRSDRAM controller,,blocks generated by MIG coregen

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