Synthesis Puzzles
The more I try to understand the Verilog synthesis tool behavior, the less I understand it. I decided to go back to square 1 with my design, and start by implementing a basic 8-bit counter that can be reset, loaded,…
128 Is Not Enough
With more work, I was able to further squeeze the design down to 77 macrocells! You can grab the latest version of the Verilog files here.Unfortunately, when I then started to add the X register and its related functionality, things…
8-Bit CPU Comparison
BMOW’s instruction set was a close cousin to the 6502’s, and so when I started on CPLD CPU, I initially intended to try something different. I looked at the Intel 8008 and 8080, Zilog Z80, and Motorola 6800 and 6809,…
T-Shirts
BMOW logo T-shirts are now available! Check the link on the left sidebar. Get one and show a little electronics geek pride! Available in six colors, $18.99 each, operators are standing by to take your order. These are the same…
Feeds
If you’re not reading the BMOW comments, you’re missing half the discussion. Matthew Simmons asked if there’s a comments feed, and the answer is YES. I’ve added links for both the posts and comments feeds to the left sidebar. I…
Birth of a CPU
I’ve finished the basic guts of the CPLD CPU, and it works! It’s still missing roughly half of the intended CPU functionality, but what’s there now is still a usable CPU. I’ve implemented jumps, conditional branching, set/clear of individual ALU…
Separated at Birth
I’ve been planning to use an Altera Max 7128S for this CPLD – CPU project, because at 128 macrocells it’s the largest commonly-available CPLD that I could find in a PLCC package. Yesterday, however, I started wondering how the competition…
Verilog Examples Synthesized
I decided to take the advice I gave myself in the comments of my previous post, and actually synthesize the three Verilog adder examples to see what would happen. I tried each of the examples under Quartus II Web Edition…
Verilog Headaches
I’m having some trouble finding the best way to structure the Verilog code for this CPU. In particular, I’ve encountered one small headache and one larger one. The small headache relates to the best way to describe complex combinatorial logic…
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