Since the Plus Too project hasn’t seen any progress in a year, I’m posting all the design files in the hopes that someone else may want to build on what I’ve done. If you missed the earlier discussions about it, Plus Too is a working replica of a Macintosh Plus, implemented in an FPGA.
Download the Plus Too file archive
What You’ll Need
- An Altera DE1 FPGA development board
- A Windows-based PC
- An old PS/2 mouse from a PC (newer USB-based mice won’t work)
- A VGA monitor capable of displaying 1024 x 768 @ 60Hz
- Download the Control Panel configuration file DE1_USB_API.sof into the FPGA. This file is included on the CD that comes with the DE1 kit. See sections 3.1 and 4.1 of the DE1 user manual for help.
- Run the DE1_Control_Panel.exe program on your PC. This is also included on the DE1 CD.
- Click on the Flash tab.
- Click the Chip Erase button to clear the DE1 Flash memory.
- In the Sequential Write section, enter 0 for the address and click the File Length checkbox.
- Click the Write a File to Flash button. When prompted, select the plusrom.bin file from the Plus Too archive, and write the file to the DE1 memory. This is a ROM dump from Macintosh Plus.
- In the Sequential Write section, enter 20000 (hex) for the address. Confirm the File Length checkbox is still checked.
- Click the Write a File to Flash button. When prompted, select the Disk608-800K.bin file from the Plus Too archive, and write the file to the DE1 memory. This is a System 6.0.8 boot disk image.
- Download the Plus Too configuration file plusToo_top.sof into the FPGA. This is included in the Plus Too archive.
You should now be up and running! Connect a PS/2 mouse and a VGA monitor for some retro-computing fun.
Using Plus Too
There’s no support for the keyboard, sound, or SCSI. The floppy disk is read-only.
Watch out! There’s a bug somewhere that causes PlusToo to crash or the mouse to stop working (not sure which) if you move the mouse around too much or too fast. I’m still not sure what the cause is, but I wrote about it more in a previous post.
Along the bottom of the screen you’ll see some debug information, shown in green text. From left to right, these are:
- A – the current value on the address bus
- D1 – the incoming value from the data bus
- D0 – the outgoing value from the data bus
- (not labeled) – the current interrupt level
- AA – the previous value of the address bus
- B – the breakpoint address
You can set the breakpoint address using the DE1 switches. When the current address equals the breakpoint address, Plus Too will halt.
The hardware can be controlled using the four push-button switches on the DE1 board, which are labeled Key0 through Key3, as well as the 10 slide switches labeled SW0 through SW9.
- Key2 inserts a blank disk into the external drive. Useful for debugging only.
- Key1 inserts the System 6.0.8 disk into the internal drive.
- Key0+Key1 together perform a reset.
- SW0 selects between free-running (switch down) and single-step mode (switch up).
- When in single-step mode:
- Key0 performs a step
- Key1, Key2, and Key3 load the low, middle, and high bytes of the breakpoint address from switches SW9-SW2.
Making Floppy Disk Images
The Disk608-800.bin file is not a standard floppy disk image file such as you would use with a Mac emulator like Mini vMac or Basilisk II. It’s an encoded file containing data exactly as it would appear on a real floppy disk, complete with sector markers, checksums, and inter-sector timing gaps.
If you want to take an 800K floppy image from your favorite emulator and use it with Plus Too, you’ll need to encode it using my Floppy Encoder utility. It takes a normal floppy image file as input, which usually has a .dsk filename extension, and generates an encoded image file with a .bin extension. The resulting .bin file can then be substituted in step 8 of the setup instructions to run Plus Too with the new floppy image.
Extending Plus Too
The Verilog source files are included in the file archive, for anyone who wants to try taking the project further. The biggest thing it needs now is for someone to set up proper timing constraints. I played around with it a bit, but I didn’t really understand the constraint editor and was eager to move on. PlusToo mostly works without specifying any constraints, but sometimes it will randomly fail to boot up, or exhibit bizarre video bugs. I’ve found that changing the number of signals and sample depth of the Signal Tap logic analyzer setup can fairly predictably make such problems appear and disappear.
The constraints should be:
- External 50 MHz clock
- Internal 32.5 MHz clock synthesized with a PLL. This is the video clock, called clk32 in the Verilog source.
- Internal 8.125 MHz clock named clk8, derived from clk32 with a clock divider. (I couldn’t make this work with a PLL)
- Flash ROM has an address-to-data delay of 70ns. The total delay from clk8 to when all the Flash control and address lines are stable, plus 70 ns, plus whatever the setup time is for the FPGA registers that will receive the Flash data (how do you determine this?), must be less than the clock period of 123ns.
- Similarly for the SRAM, except I believe its address-to-data delay is 10ns (check datasheet). The SRAM should also have additional constraints for write timing.
Read 16 comments and join the conversation