Cramming Everything In
I’ve made a little bit of progress on the CPU in a CPLD project. As mentioned previously, this will be an 8-bit CPU with a 10-bit address space, targeting a 128 macrocell CPLD. The instruction set will be a simplified version of BMOW’s, which itself was a close cousin of the 6502 instruction set. Exactly how “simplified” it needs to be in order to fit remains to be seen, but I’m planning to omit the Y register, zero page, and indirect addressing modes. It will still have A and X registers, a hardware stack pointer, and all the “standard” opcodes in immediate, absolute, and indexed addressing modes. I’ve mostly just been planning and not writing much Verilog yet, but after fleshing out the datapath and a tiny bit of control logic, I’ve used 73 macrocells so far.
Working with the Altera software has been pretty good so far, and I’ve been much less frustrated than when I was working with the Xilinx software to create 3DGT from an FPGA. I’m not sure if that’s the software itself, or simply that I’m working on a simpler project and a simpler device, but it’s a welcome change.
I found a couple of similar CPU projects that might provide some inspiration:
MCPU – http://www.opencores.com/project,mcpu – A very tiny CPU that fits in a 32 macrocell CPLD. It has a single 8-bit register, and just a 6-bit (64 word) address space. It also has only four instructions: NOR, ADD, store, and conditional jump. Yet with combinations of those instructions, you can do some pretty complicated stuff. Very clever! Check it out.
MPROZ – http://www.unibwm.de/ikomi/pub/mproz/mproz_e.pdf – MCPU borrows its instruction set from here. MPROZ has a 15-bit address space, but NO data registers. All computation is done directly on locations in memory. It also does MCPU one better by having only three instructions: NOR, ADD, and branch. It fits in an FPGA with 484 macrocells.
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It seems I probably don’t need a phase register after all, as I’d first thought. BMOW’s phase register was used as an index into microcode, but this CPU won’t have any microcode. The instruction logic will be driven by a state machine, so I’ll need a state register. I don’t think there’s any advantage to having both phase and state registers, but I’ll give it some thought.
I also think I probably won’t need an opcode register! That seems counter-intuitive, but if the state machine is built correctly, then the opcode being executed should be implied by the current state. I still may want to preserve some bits of the opcode, to better handle similar instructions whose first several states are the same, but later states diverge. Then the state machine could test those bits to determine which state to transition to.