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Tiny CPU Board Design

Whew! It was a big job, but I finished the Eagle board layout for the new Tiny CPU, using the Max II CPLD. The board is about 4×3 inches, and if your monitor has a typical 72 DPI, then the image to the left is actual size. It’s clear that soldering the 100 pins on the Max II is going to be a challenge. Click the image to see a higher-resolution version of my horrible component placement and routing.

Routing all those connections was a long, difficult job. You can see I left myself lots of extra space around the CPLD to help with routing, but the space between the CPLD, RAM, and ROM is still packed to the roof with traces.

I’m happy I was able to get all the traces to fit, since part-way through the task, success looked doubtful. Unfortunately I was forced to abandon the goal of routing all unused I/O pins to an expansion header, because I simply ran out of room. I managed to route 18 I/Os to the header, but the remainder of the unused I/Os are unconnected and unusable.

I’ll probably sit on this for a day or two, giving myself a chance to remember any last-minute stuff I forgot, before sending it to a board house for manufacturing. I’ll probably go with Seeed Studio this time, since ten copies of this 8x10cm board with 50% E-Test are only $25. Having ten copies will be a big help, when I melt the first few trying to solder those nano-scale pins!

Read 11 comments and join the conversation 

11 Comments so far

  1. ian - June 4th, 2011 12:08 am

    NIce work. I was going to leave a comment to watch out for the keyboard’s internal pull-ups to 5volts, but it was the first comment on the previous Tiny CPU post. Does the max II have 5volt tolerant pins, or how did you handle the keyboard level translation?

  2. Steve - June 4th, 2011 7:12 am

    No, the Max II does not have 5v tolerant inputs. I’m using a 74LVC08 for level conversion (upper-right, next to the LCD header). It’s just a 2-input AND gate, which is unimportant for my purposes, but it’s a 3.3v chip with 5v tolerant inputs.

  3. Steve - June 4th, 2011 8:20 am

    I just realized I made a huge mistake. The PLCC flash ROM (left-center) was supposed to go in a PLCC socket, so it could be removed and programmed in my stand-alone programmer. Instead, I used the footprint for a naked PLCC with no socket. DOH!

    I think I’m going to leave it as is. All the ROM’s pins are connected to the CPLD. It should therefore theoretically be possible to program the ROM using JTAG parallel flash programming (had some difficulty with this in the past), or by making some kind of ROM programming circuit in the CPLD and bit-banging it through the serial port or expansion header.

  4. John Burton - June 5th, 2011 12:04 am

    What is the rom for?
    I thought that the max II devices were non-volatile and could be programmed directly? I may be wrong. Or is the rom for something else?

  5. Steve - June 5th, 2011 7:20 am

    The Max II non-volatile memory holds the CPLD configuration, which defines the CPU itself. The ROM stores the CPU’s program, just like a regular computer.

  6. John Burton - June 5th, 2011 9:39 am

    ah right that makes sense.

  7. Erik Petrich - June 6th, 2011 9:01 am

    There also are PLCC sockets that are designed to surface mount to a PLCC footprint. However, they are insanely difficult to solder by hand since the pads on the PCB are hard to get to with the socket in place. I have successfully soldered the 100 pin PQFP chips, but my attempts at soldering these style of sockets have been failures. I realize you’re already planning to do indirect programming via JTAG, but I thought I would mention my experience in case you saw these sockets later.

  8. trevor - June 10th, 2011 4:17 pm

    This looks awesome! Where can I find all the gritty details???

    For example, the assembler instructions list.. assuming of course there’s no compiler 😉

    What software tools are needed? Max Plus? Quartus v? Can the cpu source code be downloaded/modified? (Is it verilog, vhdl, schematic, ahdl)?

    Is it possible to do debugging of the software via the jtag (like the nios environment)?

    Also, I don’t have the tools (nor skills) to solder the pqfp pitch… will assembled boards be available for sale??

  9. Steve - June 10th, 2011 6:31 pm

    More info on the Tiny CPU design (including Verilog source and the assembler program) are at

    This is a personal project, not something intended for 3rd-party use, but if there’s enough interest I could see making it into a kit. Keep in mind I haven’t even built one yet– still waiting for the PCBs to come back from the board house!

  10. dff - October 11th, 2011 3:19 am

    Looks like you added a power plane on top side of the board and ground plane on the bottom side. Was there any particular reason for that? Is it generally a better idea to have a vcc plane and a ground plane, rather than having two ground planes?

  11. Steve - October 11th, 2011 6:14 am

    I have no idea! It just made sense to me to have one power and one ground plane, but I don’t know if it’s standard practice for people who do this professionally.

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